1. Field of the Invention
The present invention pertains to the field of high speed telecommunications transceivers; and specifically, to the field of testing high speed telecommunication links using the transceiver circuitry.
2. Background of the Invention
In many telecommunications applications, line loop-back mode is used to test the serial high-speed link between two locations. A stream of serial bits is sent over the link, fiber optics for example, to a receiver, which sends it directly to the transmitter and sends it back over the link to the original sender. The sender compares the transmitted and received data, and, if they match, the link must be functional. Such loop-back mode typically requires high speed multiplexers and buffers which are not only very difficult to implement, but also consume a great deal of power and degrade jitter performance of the normal mode operation.
FIG. 1 illustrates general line loop back 100 signal flow. A sender (not shown) sends an optical signal 101 over the link 102. The signal 101 is received by the receiver 103 and passed to the transmitter 105 through a line loop back connection 104 between the receiver 103 and transmitter 105. The transmitter 105 sends an equivalent signal 106 back right away through the link 107. The purpose of the general line loop back mode is to be able to test the links 102 and 107 themselves. The testing sender sends signal 101 then compares the looped back signal 106 to the original signal 101. If the sent signal 101 matches the looped back signal 106, then the lines 102 and 107 are functioning properly. A typical implementation for a line loop back test is on an integrated circuit itself having a receiver 103 and a transmitter 105. The receiver 103 receives the optical serial data on its input 108, converts the data to a lower speed parallel form, and then sends the lower speed parallel data through parallel output port 109 to another application specific integrated circuit (not shown) which performs further processing on the parallel data. Typically, either the same or another application specific integrated circuit feeds the transmitter 105 lower speed parallel data through input port 110.
As is apparent from the above discussion, a need exists for a telecommunications circuit suitable for transceivers that provides for cost-effective and efficient implementation of the line loop back test which is not difficult to implement, conserves power, and which does not adversely affect the jitter performance of normal mode transceiver operation.